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What is VHDL?
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Course preview: I²C controller for interfacing a real-time clock/calendar module in VHDL
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How I came up with the VHDLwhiz Membership
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How to use the most common VHDL type: std_logic
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Course preview: VHDL synthesis: From code to hardware
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How to use an Impure Function in VHDL
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Why I created the VHDLwhiz Membership instead of another course
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How to create a Finite-State Machine in VHDL
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VHDLwhiz Membership "unboxing" - November 2021
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How to use Loop and Exit in VHDL
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Course preview: SPI master for reading ambient light sensor
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How to stop simulation in a VHDL testbench
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How to use Port Map instantiation in VHDL
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How to create a signal vector in VHDL: std_logic_vector
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What's inside the VHDLwhiz Membership portal?
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